`timescale 1ns / 1ps
/******************************************************************************
*                                                                             *
* UTICA softcore v0.1                                                         *
*                                                                             *
* Copyright (c) 2012 Andrew D. Zonenberg                                      *
* All rights reserved.                                                        *
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* Redistribution and use in source and binary forms, with or without modifi-  *
* cation, are permitted provided that the following conditions are met:       *
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*      specific prior written permission.                                     *
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******************************************************************************/

/**
	@file BoardHealthMonitor_UARTWrapper.v
	@author Andrew D. Zonenberg
	@brief Board health monitor - to - UART bridge
 */
module BoardHealthMonitor_UARTWrapper(
	clk,
	vbus_3v3, vbus_2v5, vbus_1v2,
	ibus_3v3, ibus_2v5, ibus_1v2,
	pbus_3v3, pbus_2v5, pbus_1v2,
	uart_tx, uart_rx
    );
	 
	///////////////////////////////////////////////////////////////////////////////////////////////
	// IO declarations
	 
	input wire clk;
	 
	input wire[15:0] vbus_3v3;
	input wire[15:0] vbus_2v5;
	input wire[15:0] vbus_1v2;
	input wire[15:0] ibus_3v3;
	input wire[15:0] ibus_2v5;
	input wire[15:0] ibus_1v2;
	input wire[15:0] pbus_3v3;
	input wire[15:0] pbus_2v5;
	input wire[15:0] pbus_1v2;
	
	input wire uart_rx;
	output wire uart_tx;

	///////////////////////////////////////////////////////////////////////////////////////////////
	// The UART

	reg[7:0] uart_txin = 0;
	reg uart_txrdy = 0;
	wire uart_txactive;
	
	wire[7:0] uart_rxout;
	wire uart_rxrdy;	

	reg[15:0] clkdiv = 16'd694;	//115.2 kbaud @ 80 MHz
	
	UART uart (
		.clk(clk), 
		.clkdiv(clkdiv), 
		.tx(uart_tx), 
		.txin(uart_txin), 
		.txrdy(uart_txrdy), 
		.txactive(uart_txactive), 
		.rx(uart_rx), 
		.rxout(uart_rxout), 
		.rxrdy(uart_rxrdy)
		);
		
	////////////////////////////////////////////////////////////////////////////////////////////////
	// Control code
	
	reg[3:0] regid = 0;
	reg[15:0] txbuf = 0;
	
	localparam STATE_IDLE = 0;
	localparam STATE_SENDHI = 1;
	localparam STATE_SENDLO = 2;
	localparam STATE_WAIT = 3;
	
	reg[1:0] state = STATE_IDLE;
	
	reg bytenum = 0;
	
	reg[17:0] wait_timer = 0;
	always @(posedge clk) begin
	
		uart_txrdy <= 0;
		uart_txin <= 0;
	
		case(state)
			
			//decide what to send
			STATE_IDLE: begin
				if(uart_txactive || uart_txrdy) begin
				end
				
				else begin
					
					case(regid)
						0: txbuf <= 16'h1234;	//sync signal
						1: txbuf <= 16'h5678;
						2: txbuf <= 16'h9abc;
						3: txbuf <= 16'hdef0;
						4: txbuf <= 16'h5555;
						
						5: txbuf <= 16'h0F80;	//TODO: real power supply temperature (15.5C sample value)
						
						6: txbuf <= vbus_3v3;
						7:	txbuf <= vbus_2v5;
						8:	txbuf <= vbus_1v2;
						9: txbuf <= ibus_3v3;
						10: txbuf <= ibus_2v5;
						11: txbuf <= ibus_1v2;
						12: txbuf <= pbus_3v3;
						13: txbuf <= pbus_2v5;
						14: txbuf <= pbus_1v2;
						
						15: txbuf <= 16'h0580;	//TODO: real ambient temperature (5.5C sample value)
						
						default: txbuf <= 16'hcccc;
					endcase
					
					regid <= regid + 1;
					state <= STATE_SENDHI;
					
					if(regid == 15) begin
						state <= STATE_WAIT;
						wait_timer <= 1;
					end
				end
			end
			
			//send high order byte
			STATE_SENDHI: begin
				if(uart_txactive || uart_txrdy) begin
				end
				else begin
					uart_txrdy <= 1;
					uart_txin <= txbuf[15:8];
					state <= STATE_SENDLO;
				end
			end
			
			//send low order byte
			STATE_SENDLO: begin
				if(uart_txactive || uart_txrdy) begin
				end
				else begin
					uart_txrdy <= 1;
					uart_txin <= txbuf[7:0];
					state <= STATE_IDLE;
				end
			end		
			
			STATE_WAIT: begin
				wait_timer <= wait_timer + 1;
				if(wait_timer == 0)
					state <= STATE_SENDHI;
			end
			
		endcase
	
	end

endmodule
